Loading verilog file '/net/redfox.ece.Virginia.EDU/isan0/users/mkc5dm/Documents/synopsys/syn_tut/formality_32/pre_lay/source/Johnson_count.v'
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*********************************** Analysis Results ***********************************
Found 2 Unmatched Cone Inputs
--------------------------------
Unmatched cone inputs result either from mismatched compare points
or from differences in the logic within the cones. Only unmatched
inputs that are suspected of contributing to verification failures
are included in the report.
The source of the matching or logical differences may be determined
using the schematic, cone and source views.
--------------------------------
r:/WORK/Johnson_count/SCANOUTPORT
    Is globally unmatched affecting 1 compare point(s):
        i:/WORK/Johnson_count/SCANOUTPORT

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i:/WORK/Johnson_count/out_reg[7]/\*dff.00\*
    Matched with cell r:/WORK/Johnson_count/out_reg[7]
    Exists in the impl cone but not in the ref cone for 1 compare point(s):
        r:/WORK/Johnson_count/SCANOUTPORT

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Found 1 Directly Undriven Reference Port
--------------------------------
Output ports may be left undriven in the reference because the matching
implementation ports driven by inserted test scan logic. Those ports
cannot be verified by Formality.
You can disable verification of all undriven reference ports with this command:
'set verification_verify_directly_undriven_output false'
Verification of individual ports can be disabled as suggested.
--------------------------------
r:/WORK/Johnson_count/SCANOUTPORT
     Try adding this command before verify:
         set_dont_verify -type port r:/WORK/Johnson_count/SCANOUTPORT
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